Generally, a clock in a system or a circuit is used as a reference for operation timing, or used to guarantee fast operation without error. When an external inputted clock is used inside the system or the circuit, time delay(or, clock skew) happens due to the internal circuit. Therefore, a DLL(Delay Locked Loop) is introduced to compensate such a time delay so that an internal clock can have same phase as the external clock. That is, the DLL fits output timing of data, that is sensed by using the external clock and outputted through an output buffer, to the timing of the external clock.
It will be described for an example where the DLL is applied in a DDR SDRAM in the prior art.
FIG. 1 provides a block diagram of a register controlled DLL of a DDR SDRAM in the prior art.
The register controlled DLL of the DDR SDRAM in the prior art comprises a clock buffer unit 11, a clock divider unit 12, a dummy delay line unit 13, a delay modeling unit 14, a phase comparator unit 15, a delay controlling unit 16 and a delay line unit 17. The clock buffer unit 11 receives an external clock signal clk, clkb to its input to generate internal clocks rclk, fclk that are synchronized to the rising edge and the falling edge of the external clock signal clk, clkb. The clock divider unit 12 divides the external clock clk to 1/n(n being a positive integer) to output a reference clock ref. The dummy delay line unit 13 receives the reference clock ref as its input. The delay modeling unit 14 receives the output clock fbk_dly from the dummy delay line unit 13 to make it go through the same condition as the actual clock path. The phase comparator unit 15 compares the phase of the output fbk of the delay modeling unit 14 to that of the reference clock ref to output a shift control signal. The delay controlling unit 16 outputs a signal for shifting the clock phases of the delay line and the dummy delay line in response to the shift control signal from the phase comparator unit 15. The delay line unit 17 shifts the internal clocks rclk, fclk based on the output signal from the delay controlling unit 16.
It will be described for each part of the DLL in detail.
FIG. 2 is a detailed circuit diagram of the clock buffer unit 11 in the prior art.
The clock buffer unit 11 as shown in FIG. 2 receives the external clock clk, clkb to a differential comparing circuit to generate the internal clock rclk that is synchronized to the rising edge of the external clock. There is included a separate clock buffer for the dummy delay line unit that will be well understood by the skilled person in the art. Therefore, its detailed description will be omitted for sake of simplicity.
FIG. 3 describes a detailed circuit diagram of the clock divider unit 12 in the prior art.
The clock divider unit 12 as shown in FIG. 3 divides the frequency of the external clock to ⅛. Here, the reason why the external clock is divided is for reducing power consumption. The operations of the clock divider circuit will be well understood by the skilled person in the art. Therefore, its detailed description will be omitted for sake of simplicity.
FIG. 4 shows a detailed circuit diagram of the phase comparator unit 15 in the prior art.
The phase comparator 15 compares the phase of the input clock to that of the output clock to detect the phase difference between the two clocks. The phase comparator unit 15 compares the phase of the reference clock from the clock divider unit 12 to that of the feedback clock fbk from the delay modeling unit 14. Based on the comparison result, one of lead, lag and locking information is outputted to the delay controlling unit 16. Referring to FIG. 4, shifting right is performed depending on the comparison signals PC1, PC3 and shifting left is performed depending on the comparison signals PC2, PC4. Further, it is determined whether the shift operation is performed by using the un-divided clock rclk or by using the divided reference clock based on comparison between the reference clock ref and the feedback clock fbk. That is, if the phase difference between the reference clock ref and the feedback clock fbk is greater than the delay time of a long delay cell, the comparison signal PC5 or the signal PC6 becomes ‘H’ state. In turn, AC that is logic sum of the signal PC5 and the signal PC6 becomes the ‘H’ state and is logically combined with the un-divided clock rclk to come out of the phase comparator 151 to operate a shift register control signal generator 152 and a T-F/F(flipflop). In other words, when the phase difference between the reference clock ref and the feedback clock fbk is great, that phase difference is to be reduced fast by operating the shift register with the un-divided clock. Upon reducing the phase difference to a predetermined level, the two signals PC5, PC6 are made to go to the ‘H’ state to operate the shift register with the divided clock.
FIG. 5 represents a detailed circuit diagram of the delay control unit 16 in the prior art.
The delay control unit 16 is constructed by one part for determining the input path of the clock in the delay line unit and the other part including a bi-directional shift register for changing the path position. The shift register in the delay controlling unit 16 performs the shift operation by using 4 input signals and has a maximum or minimum delay by making its initial input condition such that its most right signal or most left signal is in the ‘H’ state. The input signals to the shift register are a shift right even signal, a shift right odd signal, a shift left even signal and a shift left odd signal. For shift operation, two of the signals in the ‘H’ state should not be overlapped.
FIG. 6 illustrates a detailed circuit diagram of the delay line unit 17 in the prior art.
The delay line unit 17 is a circuit for delaying the phase of the external clock. Here, the amount of the delay is determined by the phase comparator 15, and the delay line unit 17 forms a delay path that determines the phase delay under control of the delay controlling unit 16. The delay line unit 17 includes a number of unit delay cells that are serially coupled to each other. The unit delay cell includes 2 NAND gates that are serially coupled to each other. The input of each of the unit delay cells is connected to the shift register in the delay controlling unit 16 in one-to-one mapping, where only one of the shift registers outputs the ‘H’ state to have the path for the reference clock. The delay line unit 17 is constructed with 2 delay lines of one delay line for the rising clock and the other delay line for the falling clock in the DDR SDRAM to suppress duty ratio distortion as much as possible by identically processing the rising edge and the falling edge.
Through a particular circuit is not shown, the dummy delay line unit 13 is a delay line for feedback clock that is inputted to the phase comparator unit 15 and its constitution is similar to that of the delay line unit 17 in FIG. 6 except that the divided clock is inputted to the dummy delay line unit 13 so that power consumption can be reduced. The delay modeling unit 14 models the front part of the delay line unit 17 from the input of the external clock to a chip, and delay factors that the output clock of the delay line unit 17 goes through till the output clock exits the chip. The clock signal line is a path that the clock goes through from the delay line unit 17 to an output buffer. The output buffer synchronizes data to the clock on the clock signal line to output the data through an external output port.
The DLL as described above continuously compares the external clock to the internal clock to synchronize the two clocks, and detects information about the phase difference between the two clocks to adjust the delay lines to reduce the phase difference. However, if noise is not considered in the DLL, there should exist a phase error due to the resolution of the unit delay cell, i.e., a skew, to make locked only with the phase error of the resolution of the unit delay cell. Once the noise is considered, a jitter due to the noise should be considered in addition to the skew.
The jitter occurs due to thermal noise and flicker noise in addition to external or internal power noise. Due to the jitter, in the phase comparator of the DLL, locking point varies with continuous comparison of the two clocks. Though that variation of the locking point could compensate the external or internal noise, but cannot compensate the difference between the comparison time of the phase comparator and the generation time of the actual noise. In this reason, a phase margin is introduced to a PLL(Phase Locked Loop) or the DLL.
FIG. 7 shows a diagram for exemplifying case by case a reaction time and applying time of the noise that occurs in the DDL circuit in the prior art.
The noise occurs before the delay lines and at the phase comparator and replica model.
First, it will be described for the delay due to the noise that occurs before the delay lines (Hereinafter, it will be called as a first delay factor). The first delay factor is generated due to the power noise of the delay lines, the thermal noise of transistors and the flicker noise.
Assuming that the point when the amount of the delay starts to vary due to the noise is 0, the clock is inputted to the replica model 14 at a delayed timing ‘Tclk−td2’ (For locking of the DLL, Tclk is the clock period and td2 is the delay time of replica) after passing the dummy delay line 13. Then, the clock is inputted to the phase comparator at ‘Tclk’ delayed timing after passing the replica model 14. That is, after ‘Tclk’, delay compensation is performed at the phase comparator unit 15. Because the result of the phase comparator unit 15 should have more delay with passing the register controller and the shift register in the delay controller 16, the actual timing when the delay compensation is applied to the delay lines is at least after 2Tclk when there is no low-pass-filter used, but the actual timing will be even more delayed when there is any low-pass-filter used. In other words, due to the first delay factor, there will be a delay of 2Tclk through the dummy delay line 13, the replica model 14 and the delay controller 15.
Next, it will be described for the delay due to the noise that occurs at the replica model (Hereinafter, it will be called as a second delay factor). The reason for occurrence of the second delay factor is similar to that of the first delay factor.
If the replica model 14 is equal to noise environment, the delay at the replica model 14 should be varied depending on the noise occurrence timing. However, assuming that the noise occurrence timing at the replica model 14 is 0, the clock is inputted to the phase comparator 15 at a ‘td2’ delayed timing after passing the replica model 14 and the delayed clock from the phase comparator 15 is delayed again passing the register controller and the shift register in the delay controller 16. Therefore, because the delay time in the delay controller 16 is greater than Tclk, the actual timing when the delay compensation is applied to the delay line 17 is after ‘Tclk+td2’, but the actual timing will be even more delayed when there is any low-pass-filter used. In other words, due to the second delay factor, there will be ‘Tclk+td2’ delay through the replica model 14 and the delay controller 15.
Finally, it will be described for the delay due to the noise at the phase comparator unit 15 (Hereinafter, it will be called as a third delay factor).
Though the phase comparator unit 15 is robust to the noise compared to other circuits, it would be affected by the noise due to mismatch between the paths of the feedback clock fbk and the reference clock ref on the layout and uncertainty window. Because that noise goes through the register controller and the shift register of the delay controller 16, the dummy delay line 13, the replica model 14 and the delay controller 16, it results in ‘3Tclk’ the greatest response time.
On the other hand, the way to compensating the delay due to the noise to the DLL is blocking the noise or reducing the response time of the DLL. Here, the response time reducing method is for reducing the time before the delay lines is varied based on the information from the phase comparator. However, such a reducing method has a limitation because there always exists a delay time occurring at the other delay line and the replica model even though the response time is 0. Actually, for the low-pass-filter, opposite noise occurs when the delay line has been varied with the result from the phase comparator due to the noise and, in turn, due to that opposite noise, the delay line is to be varied in the opposite direction against the typical direction so as to generate a jitter that is 2 times greater than typical. That is, when the jitter due to the typical noise is ‘t_jitter’, the delay line compensates that ‘t-jitter’ but, if additional noise ‘−t_jitter’ occurs at that time, there happens very serious noise of ‘−2t_jitter’.